1. Field of the Invention
The present invention relates to a microprocessor, and more particularly, to a microprocessor by which debugging at the time of developing software is facilitated, and a real time software developing environment can be provided.
2. Description of the Related Art
In general, when developing software by using a microprocessor, as a process of debugging programs, the process of providing some breakpoints in steps during execution of the programs is adopted. In case of providing the breakpoints on the program as such, since processings are broken temporarily at the time point when program execution passes the breakpoint, whenever the break occurs, an execution history of the microprocessor is checked before proceeding to the following program executions.
In some cases, though the breakpoint is provided per instruction in an initial step of software development, the breakpoints are generally provided for certain definite number of instructions as a unit as the debugging proceeds, particularly, when the breakpoint is provided in a unit of subroutine to check the instruction execution history, it is possible to grasp a processing flow of the entire softwares.
Meanwhile, when the execution history of a plural number of subroutines can be checked, it can be debugged efficiently.
FIG. 1 is a block diagram showing an example of configuration of a conventional microprocessor.
In FIG. 1, numeral 11 designates a microprocessor comprising, an instruction fetch unit 12, an instruction decoding unit 13, an instruction executing unit 14 and an information saving control unit 17. A memory M is disposed outside the microprocessor 11, and is connected thereto through an address bus 15 and a data bus 16.
The instruction fetch unit 12 fetches an instruction to be processed from the memory M outside the microprocessor 11 via the data bus 16, and gives it to the instruction decoding unit 13.
The instruction decoding unit 13 decodes the kinds and processing formats for the instruction fetched from the memory M by the instruction fetch unit 12. The instruction is decoded by an instruction decoding circuit 23 included in the instruction decoding unit 13, and the decoded result of the instruction is given to the instruction executing unit 14 as a decoded result signal SG1.
The instruction executing unit 14 actually executes the instruction processing, according to the decoded result by the instruction decoding unit 13, more specifically, according to the decoded result signal SG1 outputted from the instruction decoding circuit 23.
The instruction executing unit 14 outputs a save direct signal SG2 to the information saving control unit 17, when executing such an instruction as to return the processing again to an original location, after once executing an instruction group stored at a separate location on the memory M from the instruction being executed at that time point, for example, such as a subroutine call instruction.
The information saving control unit 17 controls the processing of temporarily saving information necessary for returning the processing to the original location, or addresses storing a return address instruction, in the memory M via the data bus 16, when the save direct signal SG2 is given from the instruction executing unit 14, in other words, when the instruction executing unit 14 executes such an instruction as to return the processing again to the original location, after once executing an instruction group stored at a separate location on the memory M from the instruction being executed at that time point, such as a subroutine call instruction.
The aforementioned instruction fetch unit 12, instruction executing unit 14, information saving control unit 17 are interconnected through the address bus 15 and the data bus 16. The microprocessor 11, when fetches an instruction from the memory M or executes the instruction, inputs and outputs data to and from the memory M through the data bus 16, and outputs an address which directs input and output addresses of the data through the address bus 15.
FIG. 2 is a schematic view showing an example of storing state of the instruction to be executed by the microprocessor 11 on the memory M.
In this example, it is assumed that instructions D1, D2 and D3 are respectively stored in addresses A1, A2 and A3 respectively, and they are all consecutive instructions (the instruction stored in the next address is executed next). Since the respective instruction lengths of the instructions D1, D2 and D3 differ when kinds of the instructions differ from each other. For example, assuming that the length of the instruction D1 in the address A1 is L1, the address A2 of the next consecutive instruction D2 coincides with a value derived from adding L1 to the address A1, and similarly, when the length of the instruction D2 is L2, the address A3 coincides with a value derived from adding L2 to the address A2.
Next, an execution process of the instruction group as shown in FIG. 2 by the microprocessor 11 shown in FIG. 1 is described.
When actually executing the instruction, the microprocessor 11, at first, outputs the address A1 to the address bus 15 by the control of the instruction fetch unit 12, and as its response, receives data called an instruction D1 from the memory M via the data bus 16.
The instruction D1 fetched into the microprocessor 11 is decoded by the instruction decoding circuit 23 included in the instruction decoding unit 13, and the decoded result signal SG1 showing the decoded result is given to the instruction executing unit 14. The instruction executing unit 14 executes the instruction D1 according to the decoded result signal SG1 given from the instruction decoding unit 13. When data is inputted to and outputted from the outside in the execution step of the instruction D1, a responding address is outputted to the other outside address via the address bus 15, and when data is outputted, a responding data is outputted via the data bus 16, or when data is inputted, a responding data is inputted from the data bus 16.
According to the above-mentioned processing, execution of the instruction D1 is completed. When the executed instruction D1 is not the non-consecutive instruction such as a subroutine call instruction, the microprocessor 11 fetches and executes a next instruction D2 which is stored consecutively to the instruction D1. By repeating such operations, a plural number of instructions D1, D2 and D3 are executed sequentially.
By the way, a lot of recent microprocessors are so constituted as to execute the instructions in the instruction executing unit 14 by microprograms. FIG. 3 shows a block diagram of a configuration example of a processor which controls instruction execution by a microprogram system.
In the example shown in FIG. 3, a micro ROM 20 which stores the microprograms is included in the instruction executing unit 14 in the microprocessor 11, and various microprograms responding to the instructions are stored in advance in the micro ROM 20. The instruction decoding circuit 23 decodes the fetched instruction to decide an address of the micro ROM 20 in which the microprogram responding thereto is stored, and gives it to the instruction executing unit 14 as the decoded result signal SG1. Then, the instruction executing unit 14, according to the decoded result signal SG1 given from the instruction decoding circuit 23, in other words, according to the address decided by the instruction decoding circuit 23, reads the microprogram from the micro ROM 20, and controls the operation of the instruction executing circuit 21 by the microprogram to process the instruction.
In such a way, since the microprocessor adopting the microprogram system can process the different instructions by using the same instruction executing circuit, a circuit structure can be minimized. Thus, this microprogram system is used in most of the recent microprocessors.
Next, as an example of the case where discontinuity presents in the instruction to be executed, a processing method of the microprocessor 11 when the subroutine call instruction is executed, is described with reference to a schematic view of FIG. 4 showing an example of a storing state on the memory M of the instruction executed by the microprocessor 11.
In FIG. 4, assuming that the subroutine call instruction D2 is stored in the address A2, and the other instruction D1 stored in the address A1 and the instruction D3 stored in the address A3 are all consecutive instructions.
At first, the microprocessor 11 outputs the address A1 to the outside via the address 15, receives data called the instruction D1 via the data bus 16, and executes the instruction in the instruction executing unit 14 in the same manner as described before.
Then, the microprocessor 11 fetches the instruction D2 from the address A2 in which the instruction to be executed next is stored. In this case, since the instruction D2 is the subroutine call instruction for calling a subroutine S1, the information saving control unit 17 operates to save the address 3, in which the instruction D3 to be executed next when the processing returns from the subroutine S1 in the future is stored, in, for example, the memory M outside the microprocessor 11, before the processing by the instruction executing unit 14 branches to the subroutine S1. Then, the microprocessor 11 outputs an address A4 of a head instruction D4 of the subroutine S1 to the address bus 15, and fetches the instruction D4 from the data bus 16 for execution, thereby to proceed the processing of the subroutine S1.
Finally, a subroutine return instruction is stored in an address A5 as an instruction D5 at an exit of the subroutine S1, the microprocessor 11 fetches as data the address A3 which has been previously saved to the outside, and executes the instruction D3 by nominating the data as the next output address.
By the above-mentioned processing, a plural number of instructions including the subroutine call instruction are executed.
By the way, breaking an execution in a unit of subroutine when debugging the program means to break execution of the program to be debugged at an entrance of the subroutine S1. In general, a break of execution of the program is realized by placing an instruction (a break instruction) necessary to break the instruction execution on the address in which a certain instruction is stored. In other words, by substituting the original instruction with the break instruction beforehand, and executing the break instruction by the processor, execution of the program having been executed hitherto can be broken.
However, in this process, before executing the program to be debugged, the subroutine call instruction of the program to be debugged must be located sequentially and substituted with the break instruction. For this purpose, debugging softwares must include functions to decode the program to be debugged to check the location where the subroutine call instruction is stored.
Next, as another example of the case where discontinuity presents in the instruction to be executed, processing procedures by the microprocessor 11 in case of executing a plural number of subroutine call instructions continuously, are described with reference to a schematic view of FIG. 5 showing an example of storing state on the memory M of the instruction executed by the microprocessor 11.
In FIG. 5, it is assumed that subroutine call instructions D1 to Dn which are one of non-consecutive instructions are respectively stored in addresses A1 to An.
At first, the microprocessor 11 outputs the address A1 to the outside via the address bus 15, and receives data called the instruction D1 via the data bus 16. As the result of decoding of the instruction D1 by the instruction decoding unit 13, the instruction D1 is interpreted as the subroutine call instruction for calling the subroutine S1 and as the non-consecutive instruction. As a result, the information saving unit 17, before the processing by the instruction executing unit 14 branches to the subroutine S1, operates to save the address A2, in which the instruction D2 to be executed next when the processing returns from the subroutine S1 in the future is stored, in, for example, the memory M outside the microprocessor 11.
Then, for executing a head instruction S1D1 of the subroutine S1, the microprocessor 11 outputs an address S1A1 of the instruction S1D1 to the address bus 15, fetches the instruction S1D1 from the data bus 16 for execution, thereby to proceed the processing of the subroutine S1.
Finally, since a subroutine return instruction is stored in an address S1A2 as an instruction S1D2 at an exit of the subroutine S1, the microprocessor 11 fetches as data the address A2 which has been previously saved, and executes the instruction D2 by nominating the data as the next output address.
Since the instruction D2 is also the subroutine call instruction for calling a subroutine S2, or the non-consecutive instruction, the address A3 in which the next instruction D3 is stored, is saved and branched to the subroutine S2 by the same procedures. Then, by executing a subroutine return instruction S2D2 at an exit of the subroutine S2, the address A3 which has been previously saved is fetched, and the following instructions are executed by nominating the data as the next output address.
By repeating the above-mentioned operations, a plural number of subroutine call instructions D1 to Dn are executed successively.
FIG. 6 is a flow chart for explaining, procedures by a conventional microprocessor for breaking in a unit of subroutine to break the processing temporarily, and the case of executing the instruction in a state shown in a schematic view of FIG. 5 is described.
As mentioned before, breaking execution in a unit of subroutine when debugging the program means, for example, to break execution of the instruction D2 stored in the address A2, after executing the last instruction S1D2 of the subroutine is executed after the address A1 is outputted by the microprocessor 11. In general, execution of the program is broken by placing a non-consecutive instruction (a break instruction) necessary to break the instruction execution on the address in which a certain instruction is stored. In other words, by substituting the original instruction with the break instruction and executing the break instruction by the processor, the instruction processing having been executed hitherto is made non-consecutive so as to be broken.
In FIG. 6, at first, it is checked whether the instruction D1 is stored in the address A1 is the subroutine call instruction or not, and when it is the subroutine call instruction, the address A2, in which the next succeeding instruction D2 is stored, is calculated by a program routine C1 prepared for checking the length of the instruction D1 and substituting the next instruction with the break instruction (Step S51). The instruction A2 stored in the address A2 is substituted with the break instruction BD beforehand by the program routine C1 (Step S52).
When a program routine is to be processed next by execution of the break instruction BD which is the non-consecutive instruction is designated as C2, after executing the instruction D1 by an output of the address A1 or saving the address A2 to the outside (Step S53), processing the subroutine S1 (instruction S1D1) (Step S54) and executing the instruction S1D2 stored in the address A1A2, that is, fetching the saved address A2 from the outside (Step S55), the break instruction BD is executed by an output of the address A2 (Step S56), and control is moved to a program routine C2.
By the processes as stated above, only execution of the subroutine instruction groups (D1, S1) are realized. When the break instruction BD substituted in the software C2 is restored by the original instruction D2 at the end, it coincides with a usual instruction format (Step S57).
In the aforesaid description, though the case of breaking execution of one subroutine has been described, the execution break of a plural number of subroutines can be realized by repeating the similar procedures. The number of the subroutines having been passed can be obtained by calculating at every breaks.
Now, in recent years, a microprocessor including a function to support the breaking after executing all of the non-consecutive instructions is developed. In such a microprocessor, it is so constituted that, when the execution address continuity is disturbed in the instruction executing unit, the break is generated. FIG. 7 is a block diagram showing an example of configuration of such a conventional microprocessor.
The microprocessor shown in FIG. 7 has the same configuration as that shown in FIG. 1, except that a non-consecutive instruction execution break circuit designated by numeral 30 is added thereto.
The non-consecutive instruction execution break circuit 30 is provided for generating the break at the time of executing all of the non-consecutive instructions, and when the non-consecutive instruction execution break circuit 30 generates a break, a break of instruction execution is designated to the instruction executing unit 14 by a break signal 26.
Next, the operation of the microprocessor shown in FIG. 7 is described. Procedures of executing the usual consecutive instructions and the non-consecutive instruction without a break are same as the procedures of the microprocessor shown in FIG. 1, so the explanation thereof is omitted.
FIG. 8 is a flow chart for explaining procedures for temporarily breaking the processing by breaking at an entrance of the subroutine by the conventional microprocessor shown in FIG. 7, wherein instructions executed by the microprocessor 11 are stored on the memory M in the state as shown in a schematic view of FIG. 9.
That is, in FIG. 9, the consecutive instruction D1 is stored in the address A1, the non-consecutive instructions D2 which does not save information is stored in the address A2, the consecutive instruction D3 is stored in the address A3, the subroutine call instruction D4 which is the non-consecutive instruction is stored in the address A4 and the consecutive instruction D5 is stored in the address A5. The subroutine S1 starts from the instruction S1D1 stored in the address S1A1.
In the microprocessor as shown in FIG. 7, as mentioned before, a function to support a break after executing all of the non-consecutive instructions (the non-consecutive instruction executing break circuit 30) is included, to generate a break when the execution address continuity is disturbed in the instruction executing unit 14. However, in that case, a break is generated irrespective of whether or not information is saved by the information saving control unit 17. And hence, for breaking the processing only when branching to the subroutine, it is necessary to check whether or not the information has been saved.
In FIG. 8, a process of breaking the processing at the entrance of the subroutine S1 to be passed next, by execution from the instruction D1 is described.
At first, before executing the instruction, the non-consecutive instruction execution break circuit 30 of the microprocessor 11 is set to be active by the processing of the program routine C1 (Step S61).
Then, the microprocessor 11 executes the respective instructions successively (Step S62). The microprocessor 11 judges whether or not the instruction is the non-consecutive instruction (Step S63), and when the instruction is the consecutive instruction, the processing returns to Step S62 to execute the next instruction, and when the instruction is the non-consecutive instruction, the break signal 26 is outputted from the non-consecutive instruction execution break circuit 30 and the processing is broken temporarily (Step S64).
Thus, in the example in FIG. 9, though the microprocessor 11 starts execution from the instruction D1, since the first instruction D1 is the consecutive instruction, the next instruction D2 is executed. However, since the instruction D2 is non-consecutive instruction, the processing is broken.
Next, the microprocessor 11 judges whether or not the non-consecutive instruction at the time of generating the break is the instruction by which information is saved by the information saving control unit 17, by decoding an instruction format within the processing period of the program routine C2 to be executed after the break (Steps S65, S66). As a result, when it is judged that the instruction does not save information, the microprocessor 11 returns to Step S62 to process the next instruction.
Thus, in this case, though the instruction D2 is the non-consecutive instruction, as it is not necessary to save information, the microprocessor 11 executes the next instruction D3.
However, when the non-consecutive instruction at the time of generating the break requires to save information, the microprocessor 11 breaks the processing without executing the next instruction (Step S67).
Thus, when the instruction D4 which is the second non-consecutive instruction is executed, the processing is broken again, and since it is judged that the instruction D4 is the instruction to save information by the information saving control unit 17, the microprocessor 11 breaks the processing without executing the instruction S1D1 which is the instruction of the entrance of the subroutine S1 (Step S65).
When realizing the break at the time of executing the non-consecutive instruction such as the execution break in a unit of subroutine as stated above, a complicated software for decoding the instruction length, or decoding the program to be debugged to search the subroutine call instruction, or substituting the subroutine call instruction with the break instruction, must be developed, and in an area where the instruction of a ROM (read only memory) can not be substituted, this break function can not be used.
It is also problematic in that, in a microprocessor comprising non-consecutive instruction execution break means, whenever the non-consecutive instruction is executed, a real time break environment can not be realized because the processing is broken temporarily.